Microelectronic devices are packaged in multiple ways. Many forms of microelectronic devices, such as IC (integrated circuit) packages, include a substrate supporting one or more microelectronic components embedded within the substrate (i.e., retained at least partially beneath a surface of the substrate) to form at least a portion of an embedded die package.
When microelectronic devices are packaged in certain frameworks (e.g., mounted in first-die, mid-die or die-on-die architectures) they can be subject to die cracking and other stress related defects. Such defects can occur during assembly or operation (e.g., due to thermal cycling). For example, with the die-on-die architecture, once die-to-die electrical interconnections are completed along with underfill, the combination of die packages act as a single composite die package system. However, the first of the combination of the die packages may utilize high stiffness, lower CTE materials (e.g., silicon) while the second of the combination of the die packages may utilize a relatively higher CTE materials. In such situations, the first of the combination of the die packages would experience high stress and could be subject to die cracking during assembly onto the second of the combination of the die packages due to the CTE mismatch.